It is known that a semiconductor device with a super junction structure has a low ON-resistance and a high breakdown voltage. In the super junction structure, a p-type region and a n-type region are formed in a n+-type substrate and alternately arranged in a surface direction of the substrate. JP-A-2010-118536 discloses a method of manufacturing a semiconductor device with such a super junction structure for reducing a variation in the breakdown voltage.
The method disclosed in JP-A-2010-118536 is as follows. Firstly, a semiconductor substrate (i.e., semiconductor wafer) is prepared. The semiconductor substrate includes a n+-type substrate and a n−-type semiconductor layer epitaxially grown on the substrate. The semiconductor substrate has multiple chip regions partitioned along a scribe line. Then, a first oxide layer as an insulating layer is formed on a main surface of the semiconductor substrate. Next, patterning of the first oxide layer is performed so that the first oxide layer can be left only on the scribe line. Then, a second oxide layer as an insulating layer is formed on the main surface of the semiconductor substrate so that the first oxide layer on the scribe line can be covered with the second oxide layer. Thus, the thickness of the oxide layer (i.e., total thickness of the first oxide layer and the second oxide layer) on the main surface of the semiconductor substrate is largest on the scribe line.
Next, patterning of the second oxide layer is performed. Then, trenches are formed in the semiconductor substrate in a stripe pattern by using the second oxide layer as a mask. Then, wet etching is performed by using hydrofluoric acid so that the second oxide layer can be removed without removing the first oxide layer. As a result, the oxide layer (i.e., the first oxide layer) is left on only the scribe line. If the oxide layer is left near an opening of the trench, it is difficult to fill the trench with an epitaxial layer in a later process, and also it is likely that a defect occurs in the epitaxial layer.
Then, a p-type epitaxial layer is epitaxially grown over the main surface side of the semiconductor substrate so that the trenches can be filled with the epitaxial layer. As a result, a p-type region (i.e., epitaxial layer in the trench) and a n-type region (i.e., portion of the semiconductor substrate sandwiched between adjacent trenches) are alternately arranged in a surface direction of the semiconductor substrate. Thus, a super junction structure is formed.
Then, the epitaxial layer on the main surface side of the semiconductor substrate is polished and planarized by chemical mechanical polishing (CME) or the like. In this planarization process, the first oxide layer is used as a polishing stopper to reduce inclination of the polished surface with respect to the main surface of the semiconductor substrate. Thus, the distance from the polished surface to the bottom of the trench (i.e., the thickness of the epitaxial layer) can be uniform. Therefore, when the semiconductor substrate is divided along the scribe line into chips in a later process, each chip (i.e., each semiconductor device) can have almost the same breakdown voltage.
Then, after the first oxide layer and the epitaxial layer on the main surface are removed by using hydrofluoric add, a predetermined thickness of the main surface is polished away. Then, a p-type epitaxial layer is formed again on the main surface of the semiconductor substrate. Then, a standard semiconductor manufacturing process is applied to each chip region. Finally, the semiconductor substrate is divided along the scribe line into the chips. In this way, the semiconductor device with the super junction structure is manufactured.
In the conventional manufacturing method described above, the first oxide layer used as a polishing stopper in the planarization process and the second oxide layer used as a mask for forming the trench are formed in different manufacturing processes.